- state.rs: ports of mattonella_state.py (569 L), _dac_setting.py and the RegisterField byte plumbing — full 0x6C register image (64 pixel bytes, globals 0x40-0x4B, pairwise finetune-DAC nibbles 0x4C-0x6B) with exact range checks and enum parsing (ChannelMode, CalibrationTime) - mattonella.rs: port of mattonella.py (426 L) — DACInterface (enable bit 7 + 7-bit value RMW), 20 class-level descriptors, pixel batch ops (power/frontend/adj/ctrl/mask/ftdac), calibrate, full-state read/write - 9 integration tests; verified from_bytes(to_bytes(s)) == s round-trip - fake data_server moved to tests/common and fixed to advance the subaddress on multi-byte reads/writes (consecutive registers) - divergences D1-D5 documented in docs/porting-notes.md - workspace: 30 tests green